1. Field of the Invention
The present invention relates to substrate processing, and more particularly to improving the process yield using statistically dependent defect procedures and data.
2. Description of the Related Art
Currently used lithography processes are challenged to balance the Resolution, LWR and Sensitivity (RLS) performance tradeoffs while scaling resist thickness below 100 nm. Some resist material suppliers have solved the resolution problem and the dose problem, but have not been able to solve the line width roughness (LWR) requirement. This challenges the industry to have a deeper understanding of LWR as well as the RLS performance tradeoffs, so that, new hardware and processes can be designed to meet manufacturing requirements.
Many multiple patterning techniques are currently being used during semiconductor substrate processing to increase the number of features and/or structures within devices on a substrate. Multiple patterning techniques can include double exposure techniques, double patterning techniques, spacer techniques, mask techniques, and brute force techniques. In 2006, the International Technology Roadmap for Semiconductors roadmap was expanded to include double patterning a potential solution for 32 nm lithography. Multiple patterning techniques are viewed as some device manufacturers as bridge solutions that can be used until Extreme Ultra-Violet (EUV) techniques become more fully developed.
Integrated Circuit (IC) design shrinks push the limits of lithography resolution. Chemical processes become more sensitive to defects or patterning errors when pushed to the lithography limits. IC manufacturers have historically used lithography simulations and CD SEM measurements to determine the focus and dose latitude as a means to determine design rules. Optical proximity correction for mask sizing is typically driving by CD SEM measurements for absolute dimensional targeting. In addition, yield enhancement is currently being performed using defect inspection tools that are typically separated from the lithography simulation based techniques that are used for mask at each IC layer.
Furthermore, resist pattern hot spots show up as bridging or line edge roughness defects that can either short a functional part of the device, hurt the process speed/leakage, or hurt the long-term reliability of a chip. Bridging and line edge roughness “hotspots” are typically difficult to simulate due to the large number of process variations like focus, dose, temperature bake uniformity, development uniformity, etc. Accurate simulations typically require complex Monte Carlo techniques that require too much computational time to run full chip Electronic Design Automation (EDA) simulations. The IC industry typically uses image threshold techniques to determine space “hot spots” from fast optics calculations. The accuracy of these threshold techniques have improved with calibrated resist OPC models that provide some description of the resist process. However, there is no statistical description of resist response to a large number of non-ideal process effects that occur in a real manufacturing environment.